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PDS Tech Inc Electrical Design and Analysis Engineer 5 in El Segundo, California

PDS Tech, Inc. is seeking an Electrical Design and Analysis Engineer in El Segundo, CA.


  • The Electronic Products organization is seeking Senior ASIC/FPGA Verification Engineers (level 5) to support multiple product lines based in El Segundo, CA.


  • Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable test benches from scratch

  • Develop Functional Coverage Models and Closing Code Coverage

  • Utilize UVM to create drivers, monitors, predictors, and scoreboards

Required Qualifications:

  • Minimum of 14 years experience in Digital ASIC verification with at least 5 years focused on UVM

  • Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using SystemVerilog.

  • Experience with design architecture and detailed specification generation.

Preferred Skills:

  • Experience with UVMf

  • Experience with hardware emulators (Palladium, Veloce)

  • Proficiency with hardware verification languages: System Verilog, System Verilog Assertions

  • Ability to write executable test plans

  • Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.

  • Ability to create self-checking and reusable testbenches from scratch

  • Experience developing Functional Coverage Models and Closing Code Coverage

  • Proficient in scripting languages: Make, Perl, Python, etc.

  • Revision Control Systems: svn, cvs, git

  • Proficient in Linux Environments

  • Demonstrated history of 1st pass success with ASIC designs.


  • All candidates MUST hold a Bachelor's degree (or higher) in Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, disability, veteran status, age, marital status, pregnancy, genetic information, or other legally protected status.