PDS Tech Inc Design Engineer in Redmond, Washington
PDS Tech Inc. is seeking a Design Engineer, in Redmond, WA.
Implement algorithm blocks as RTL code as defined in the Micro Architecture.
Implement RTL using HLS and System Verilog.
Support DV team for verification of blocks.
Assist with synthesis and timing closure.
Work with FPGA engineers to perform early prototyping.
Support handoff and integration of blocks into larger SOC environments.
Assist with Algorithm analysis, verification and improvement.
Contribute to ASIC digital architecture, design and verification.
Ability to document and communicate clearly.
5-8 years of experience as a Digital Design Engineer.
Experience with HLS Catapult tool is a big plus but not a must.
Experience in RTL coding, Lint/CDC tools, synthesis and LEC tools.
HLS coding using Catapult and Xilinx Vivado tools.
System Verilog OVM/UVM DV experience.
Python (or similar) scripting experience.
ASIC design experience.
Masters Degree in EE.
BS Electrical Engineering/Computer Science or equivalent experience.
All qualified applicants will receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, disability, veteran status, age, marital status, pregnancy, genetic information, or other legally protected status.